CPU cache

RAM, computer memory Very good description of direct-mapped cache: pdflecture, confusing exam with good questions and answers

10 flashcards · Computer Science · by lakesare

  1. In modern CPUs there are usually multiple levels of cache, which ones?

    L1, L2, L3, L1 being the smallest and the fastest. L1 split into L1d (for data) and L1i (for instructions). L2 not split, not shared between the cores. L3 not split, shared between the cores.

  2. What's a cache line?

    == Cache entry. Groups of bits in which data is transferred between cache and RAM.

  3. What's a tag?

    Each cache entry consists of: data memory location (tag)

  4. Because there are fewer cache entries than RAM cells, and algorithm is needed for mapping RAM cells to cache entries. Name 1 such algorithm.

    direct mapping associative mapping set-associative mapping

  5. In a direct-mapped cache - what does every cache entry consist of?

  6. How do we map RAM addresses to cache addresses in a direct-mapped cache?

    cache_entry_address = RAM_block_address mod amount_of_cache_entries We add up cache entry address + tag. Links: great pdf

  7. What's direct mapping?

    Each main memory address maps to exactly one cache entry. Memory locations 0, 4, 8 and 12 all map to cache block 0. Addresses 1, 5, 9 and 13 map to cache block 1, etc.

  8. What's considered to be the size of the cache?

    Amount of data that can be stored in all cache entries. The tag, flag and error correction code bits are not included in the size, although they do affect the physical area of a cache.

  9. What's block VS page VS cache line VS hard disk block when we're talking about cache?

    block - collection of RAM cells fitting into a single cache line. page - it's about virtual memory, has nothing to do with caches cache line - one entry in cache that stores one RAM block hard disk block - collection of sectors in HDD Sometimes they call cache line a cache block. That's just how hardware is, sorry. Links: youtube video

  10. What does memory address coming into cache look like?

    index: which cache line data has been put in. The index length is log2(r) bits for r cache rows. block offset: specifies the desired data within the stored data block within the cache row. Typically the effective address is in bytes, so the block offset length is log2(b) bits, where b is the number of bytes per data block. tag: contains the most significant bits of the address, which are checked against the current row (the row has been retrieved by index) to see if it is the one we need or ano…